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AD8212
SPECIFICATIONS
V S = 15 V, T OPR = ?40°C to +125°C, T A = 25°C, unless otherwise noted.
Table 1.
Parameter
SUPPLY VOLTAGE (V+)
Conditions/Comments
No external pass transistor
With external PNP transistor 1
Min
7
7
Typ
Max
65
>500
Unit
V
V
SUPPLY CURRENT 2
(I SUPPLY = I OUT + I BIAS )
V+ = 7 V to 65 V
High voltage operation, using external PNP
220
200
720
1500
μA
μA
VOLTAGE OFFSET
Offset Voltage (RTI)
Over Temperature (RTI)
Offset Drift
T A
T OPR
T OPR
±2
±3
±10
mV
mV
μV/°C
INPUT
Input Impedance
Differential
2
kΩ
Common Mode (V CM )
V+ = 7 V to 65 V
5
MΩ
Voltage Range
Differential
Maximum voltage between V+ and V SENSE
500
mV
V SENSE (Pin 8) Current 3
V+ = 7 V to 65 V, T OPR
100
200
nA
OUTPUT
Transconductance
1000
μA/V
Current Range (I OUT )
Gain Error for T OPR
Impedance
Voltage Range
7 V ≤ V+ ≤ 65 V, 0 mV to 500 mV differential input
7 V ≤ V+ ≤ 65 V, with respect to 500 μA full scale
0
20
500
±1
V+ ? 5
μA
%
MΩ
V
REGULATOR
Nominal Value
PSRR
Bias Current (I BIAS )
7 V ≤ V+ ≤ 65 V
7 V ≤ V+ ≤ 65 V
T OPR , 7 V ≤ V+ ≤ 65 V
T OPR , high voltage operation
4.80
80
200
5
185
5.20
200
1000
V
dB
μA
μA
DYNAMIC RESPONSE
Small Signal ?3 dB Bandwidth
Settling Time
ALPHA PIN INPUT CURRENT
Gain = 10
Gain = 20
Gain = 50
Within 0.1% of the true output, gain = 20
1000
500
100
2
25
kHz
kHz
kHz
μs
μA
NOISE
0.1 Hz to 10 Hz, RTI
Spectral Density, 1 kHz, RTI
TEMPERATURE RANGE
1.1
40
μV p-p
nV/ √ Hz
For Specified Performance (T OPR )
?40
+125
°C
1
2
3
Range dependent on the V CE breakdown of the transistor.
The AD8212 supply current in normal voltage operation (V+ = 7 V to 65 V) is the bias current (I BIAS ) added to output current (I OUT ). Output current varies upon input
differential voltage and can range from 0 μA to 500 μA. I BIAS in this mode of operation is typically 185 μA and 200 μA maximum. For high voltage operation mode, refer
to the Hi gh Voltage Operation Using an External PNP Transistor section.
The current of the amplifier into V SENSE (Pin 8) increases when operating in high voltage mode. See the High Voltage Operation Using an External PNP Transistor section
for more information.
Rev. B | Page 3 of 16
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